Efficient architecture for SPIHT algorithm for compression of images [articol]

Abstract

Our work involves synthesis and FPGA implementation of high speed and high throughput Superscalar ‘Set Partitioning in Hierarchical Trees’ (SPIHT) algorithm for compression of natural images. Because of its inherent redundancy removal property among wavelet coefficients SPIHT is well suited for compression of both gray and color images. But the basic SPIHT algorithm uses dynamic data structures which hinders hardware realization. In our implementation we have used modified SPIHT. Modifications are in two ways, one by using static (fixed) mappings which represent significant information and the other by inter-changing the sorting and refinement passes. The implementation involves pipelining and parallelism operations in SPIHT blocks and peripheral circuitry. The address generation unit is designed in such a way that the coefficients of different sub bands are accessed from memory efficiently and helps in achieving higher speed and throughput. A hardware realization is done in a Altera Cyclone II FPGA development board. Significant clock speed and throughput are obtained for a test image of size 128 x128 pixels.