Negative impedance converter circuits for integrated clock transmission lines loss compensation [articol]

Abstract

The present article presents a Negative Impedance Converter (NIC) circuit that can be used for loss compensation of lossy transmission lines integrated with standard deep submicron CMOS processes. The use of standard CMOS processes places several constraints on the required performances of the NIC circuit such as the use of low supply voltages coupled with high signal swings (which limits the number of stacked transistors in circuit branches) or the appreciable working frequency (from about 1GHz to several GHz for clock signals in modern standard CMOS technologies)