A real time stereo disparity architecture for FPGA/ASIC implementation [articol]

Abstract

The paper presents an original architecture for real time stereo disparity computation. State of the art algorithms in recent reported implementations are analyzed in their adequacy to real time. For the selected SAD (sum of absolute differences) algorithm several improvements are proposed to enhance the disparity calculation. A fully pipelined design is disclosed and details of its implementation in a FPGA are presented. For the disparity computation module a weighting extension is proposed aiming to increase robustness to noise in the images. A post processing filter implementation is also described. Details of VHDL coding and synthesis are not among the objectives of the paper and only an outline is given on its feasibility.