Abstract:
The paper presents the results of a prototype FPGA implementation of a morphological multiple dimensional kernel filter for images contrast enhancement. The main objective of the work was the optimization of the silicon area and frame throughput. Operation in real time was the second constraint of the target application. A mixed schematic and VHDL/Verilog description of the decomposition filters was synthesized. The performance of the architecture was found adequate for real time conditions of operation. An extension of the architecture with a soft microprocessor for contrast enhancement calculation is also presented.
