Test pattern generation Multiple-Valued Logic Circuits [articol]

Abstract

In this paper we present a test pattern generation tool for combinational Multi-Valued Logic (MVL) Circuits. Test generation using deterministic algorithms is highly complex and time consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. Genetic Algorithms (GA’s) have been effective in solving many research and optimization problems. Since test generation is a search process over a large vector space, it is a best candidate for GA’s. The GA evolves candidate test vectors and sequences, using a fault simulation to compute the fitness of each candidate test.