dc.contributor.author |
Chiper, Doru Florin |
|
dc.contributor.author |
Teodorescu, Tiberiu |
|
dc.date.accessioned |
2021-08-31T08:15:38Z |
|
dc.date.available |
2021-08-31T08:15:38Z |
|
dc.date.issued |
2004 |
|
dc.identifier.citation |
Chiper, Doru Florin. A linear systolic array architecture for a VLSI implementation of type IV discrete cosine transform. Timişoara: Editura Politehnica, 2004 |
en_US |
dc.identifier.uri |
http://primo.upt.ro:1701/primo-explore/fulldisplay?docid=40TUT000137577&context=L&vid=40TUT_V1&lang=ro_RO&search_scope=40TUT&adaptor=Local%20Search%20Engine&tab=default_tab&query=any,contains,A%20linear%20systolic%20array%20architecture%20for%20a%20VLSI%20implementation%20of%20type%20IV%20discrete%20cosine%20transform&sortby=rank&offset=0 Link Primo |
|
dc.description.abstract |
An efficient design approach to derive a linear systolic array architecture for a prime length type IV discrete cosine transform is presented. This approach is based on a VLSI algorithm that uses a circular correlation structure. The proposed algorithm is then mapped onto a linear systolic array with a small number of I/O channels and low I/O bandwidth that can be efficiently implemented into a VLSI chip. A highly efficient VLSI chip can be thus obtained that outperforms others in the architectural topology, computing parallelism, processing speed, hardware complexity and I/O costs. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
Timişoara: Editura Politehnica |
en_US |
dc.relation.ispartofseries |
Buletinul ştiinţific al Universităţii „Politehnica” din Timişoara, România. Seria electronică şi telecomunicaţii, Tom 49(63), fasc. 1 (2004), p. 112-116 |
|
dc.subject |
Type IV discrete cosine transform |
en_US |
dc.subject |
Systolic algorithms |
en_US |
dc.subject |
Systolic architectures |
en_US |
dc.title |
A linear systolic array architecture for a VLSI implementation of type IV discrete cosine transform [articol] / |
en_US |
dc.type |
Article |
en_US |