Abstract:
An efficient design approach for a VLSI array of a prime length type III Generalized Discrete Hartley Transform (GDHT) is proposed. The presented approach uses an appropriate decomposition of type III GDHT into two cyclic convolutions having the same length and structure. The two computational structures can be implemented in parallel using the same hardware structure based on using bi-port ROMS. Using an appropriate hardware sharing technique and a VLSI architecture based on small bi-port ROMs we can obtain high computing speed with low hardware complexity and low I/O costs together with all the other advantages of the systolic array implementation of cyclic convolution as regular and modular structures with local connections.
