dc.contributor.author |
Daphne, Mary |
|
dc.contributor.author |
Thanganadar, Latha |
|
dc.date.accessioned |
2024-10-23T10:39:12Z |
|
dc.date.available |
2024-10-23T10:39:12Z |
|
dc.date.issued |
2019 |
|
dc.identifier.citation |
Daphne, Mary; Thanganadar, Latha. Combined method using NVM and SHC for space FPGAs. Timişoara: Editura Politehnica, 2019. |
en_US |
dc.identifier.issn |
1582-4594 |
|
dc.identifier.uri |
https://dspace.upt.ro/xmlui/handle/123456789/6807 |
|
dc.description.abstract |
In space application, the devices are required to retain data even when there is no power available. For that nonvolatile Memory, flash memories are used. But they have the limitation of onetime programming capability. Recently all FPGAs in space utilizes multi time programming SRAM technology but introducing soft errors in data and parity of these memories is the major issue for long-term retention. In this paper, to remit, the soft errors non-volatile SRAM Memory is proposed, and for encoding encode-and-compare scheme is built with 2-D Symbolic Hamming Matrix Code. To reduce leakage power, a low power memory cell has been used which uses positive ground voltage. The proposed method requires a short time for detecting the error and it has the capability to detect and correct a more number of soft errors. |
en_US |
dc.language.iso |
en |
en_US |
dc.publisher |
Timișoara : Editura Politehnica |
en_US |
dc.relation.ispartofseries |
Journal of Electrical Engineering;Vol 19 No 4 |
|
dc.subject |
NVSRAM |
en_US |
dc.subject |
Symbolic Hamming Matrix Code |
en_US |
dc.subject |
Reliability |
en_US |
dc.title |
Combined method using NVM and SHC for space FPGAs [articol] |
en_US |
dc.type |
Article |
en_US |