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A novel code compression approach for embedded risc processor [articol]

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dc.contributor.author Ramani, G.
dc.contributor.author Geetha, K.
dc.date.accessioned 2025-02-10T10:45:59Z
dc.date.available 2025-02-10T10:45:59Z
dc.date.issued 2019
dc.identifier.citation Ramani,G.; Geetha,K.: A novel code compression approach for embedded risc processor. Timişoara: Editura Politehnica, 2019. en_US
dc.identifier.issn 1582-4594
dc.identifier.uri https://dspace.upt.ro/xmlui/handle/123456789/7131
dc.description.abstract Now a days most of the processors are high performance RISC processors .This paper introduces a novel code compression approach for embedded RISC processor, which reduces the code size and improves the compression ratio. Code compression is the technique to reduce the program size using various code compression algorithms to original instruction sets. There are two methods of compression is used in this paper. One is Dictionary based and the other is statistical compression. Our implementation is assessed through various benchmarking performed on embedded programs. In this approach, an efficient code compression is achieved using lookup table and Canonical Huffman decoder. en_US
dc.language.iso en en_US
dc.publisher Timișoara : Editura Politehnica en_US
dc.relation.ispartofseries Journal of Electrical Engineering;Vol 19 No 1
dc.subject RISC processors en_US
dc.subject Statistical compression en_US
dc.subject Dictionary based compression en_US
dc.subject Code compression en_US
dc.title A novel code compression approach for embedded risc processor [articol] en_US
dc.type Article en_US


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