Please use this identifier to cite or link to this item: https://dspace.upt.ro/xmlui/handle/123456789/1010
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dc.contributor.authorDrăgoi, Beniamin-
dc.date.accessioned2020-03-17T11:25:23Z-
dc.date.accessioned2021-03-01T08:39:00Z-
dc.date.available2020-03-17T11:25:23Z-
dc.date.available2021-03-01T08:39:00Z-
dc.date.issued2009-
dc.identifier.citationDrăgoi, Beniamin. Procedural design of a CMOS current conveyor. Timişoara: Editura Politehnica, 2009en_US
dc.identifier.urihttp://localhost:8080/xmlui/handle/123456789/1010-
dc.description.abstractThis paper presents a new procedural design sequence for the design of a CMOS current conveyor. It is based on the structured design approach and consists in circuit partitioning, derivation of the specifications for each basic analog structure, and step-by-step design. BSIM2EKV converter is presented and EKV model is used for hand calculations. PAD (Procedural Analog Design) tool is used for validation. CCII step-by-step design is presented. Simulations (for verification and fine-tuning) using Mentor Graphics tools are presented.en_US
dc.language.isoenen_US
dc.publisherTimişoara: Editura Politehnicaen_US
dc.relation.ispartofseriesSeria electronică şi telecomunicaţii, Tom 54(68), fasc. 1 (2009);-
dc.subjectCurrent conveyoren_US
dc.subjectEKV modelen_US
dc.subjectPAD toolen_US
dc.titleProcedural design of a CMOS current conveyor [articol]en_US
dc.typeArticleen_US
Appears in Collections:Articole stiintifice/Scientific articles

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