Hardware implementation of FFT/IFFT algorithms incorporating efficient computational elements [articol]

Abstract

Fast Fourier Transform (FFT) and Inverse Fast Fourier Transform (IFFT) computation involves a quite large number of complex multiplications and complex additions. Optimizing the FFT processing elements in terms of complex multiplication reduces area and power consumption. In this work, complex multipliers in the FFT processors are replaced by area and power efficient approximate multipliers. In image and signal processing applications which can tolerate minimum error, accurate computing units are always not necessary. Accurate computing units can be replaced with approximate computing units. Approximate computing can decrease the design complexity with an increase in area and power efficiency. In this paper, approximate 8- and 16-bit multipliers are designed and implemented in radix-2 butterfly unit which is the crucial computational component in FFT/IFFT processing. The designed FFT/IFFT processing units are analyzed, synthesized and simulated in Altera Cyclone II EP2C35F672C6 FPGA device. Experimental results shows that the proposed 16-point FFT architecture incorporating approximate complex multiplier achieves an area efficiency of about 33.47% and power efficiency of 1.8% when compared to accurate 16-point FFT processor. The 8 point and 16 point Decimation-In-Time (DIT) – FFT incorporating approximate computational elements operates at a speed of 26.69Gbps and 46.20Gbps respectively.