Please use this identifier to cite or link to this item: https://dspace.upt.ro/xmlui/handle/123456789/7113
Title: An enhanced hybrid SVPWM with ann-based vector control of induction motor using FPGA [articol]
Authors: Rajan, V.R.
Selvi, K.
Subjects: Induction motor (IM)
Artificial neural network (ANN)
Variable frequency drive (VFD)
Hybrid space vector pulse width modulation (HSVPWM)
Very high speed hardware description language (VHDL)
Issue Date: 2019
Publisher: Timișoara : Editura Politehnica
Citation: Rajan,V.R.; Selvi,K.: An enhanced hybrid SVPWM with ann-based vector control of induction motor using FPGA. Timişoara: Editura Politehnica, 2019.
Series/Report no.: Journal of Electrical Engineering;Vol 19 No 1
Abstract: This scheme envisages an indirect field-oriented control that involves estimation of the rotor flux vector with the use of field-oriented control equations (current model) involving a rotor speed measurement. Up-gradation of the weights of artificial neural network used in getting optimal speed control of an induction motor has been done with the use of back-propagation algorithm. The enhanced hybrid space vector pulse width modulation (HSVPWM) technique is a blend of random pulse width modulation (RPWM) and modified space vector pulse width modulation (SVPWM) techniques considered ideal for performance improvement. Amalgamation of the resultant modified SVPWM reference and the random selection of the carrier between two triangular signals, which has, as its objectives, the disbanding of the acoustic switching noise spectrum with basic components that have gone through improvement, is the fundamental doctrine behind the suggested RPWM referred to as enhanced HSVPWM. Apart from providing an improved vector control under a dynamic change in load, the proposed scheme has also other beneficial features that include reduction in oscillations, harmonics, and switching noise in acoustics. Implementation of this scheme, which is in real time, is carried out using Spartan xc6slx45 FPGA board. Very high speed hardware description language has been used in the implementation. Proof of the viability of the proposed scheme has been provided by the results obtained from the various tests conducted.
URI: https://dspace.upt.ro/xmlui/handle/123456789/7113
ISSN: 1582-4594
Appears in Collections:Articole științifice/Scientific articles

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