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DC Field | Value | Language |
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dc.contributor.author | Anbarasan, P. | - |
dc.contributor.author | Ramkumar, S. | - |
dc.contributor.author | Thamizharasan, S. | - |
dc.date.accessioned | 2025-02-18T10:34:46Z | - |
dc.date.available | 2025-02-18T10:34:46Z | - |
dc.date.issued | 2018 | - |
dc.identifier.citation | Anbarasan,P.; Ramkumar,S.; Thamizharasan,S.: A new PWM modulated multilevel inverter topology with reduced switch count in conduction path. Timişoara: Editura Politehnica, 2018. | en_US |
dc.identifier.issn | 1582-4594 | - |
dc.identifier.uri | https://dspace.upt.ro/xmlui/handle/123456789/7195 | - |
dc.description.abstract | Multilevel Inverters proved its predominance in high voltage and medium power applications especially drive and renewable applications. Multilevel inverters have the capability of spawning stepped voltage from series of capacitor banks or isolated voltage sources through clamping diodes or capacitors. However the multilevel inverters endure huge number of power components and become complexity in control with increase in higher number of levels. A novel three phase multilevel inverter is developed to overcome aforementioned problems. The architecture is constituted using several bidirectional devices, series of isolated dc sources and high frequency transformers. The proposed structure claims minimal usage of conducting switches and one third of isolated dc sources in comparison with CHBMLI. The feasibility of the proposed MLI is validated in symmetric configurations. The simulation and experimental results are shown to prove the effectiveness of the proposed topologies under both modes. | en_US |
dc.language.iso | en | en_US |
dc.publisher | Timișoara : Editura Politehnica | en_US |
dc.relation.ispartofseries | Journal of Electrical Engineering;Vol 18 No 4 | - |
dc.subject | Multilevel inverter | en_US |
dc.subject | Symmetrical | en_US |
dc.subject | Reduced switch count | en_US |
dc.subject | Power loss | en_US |
dc.subject | PWM | en_US |
dc.title | A new PWM modulated multilevel inverter topology with reduced switch count in conduction path [articol] | en_US |
dc.type | Article | en_US |
Appears in Collections: | Articole științifice/Scientific articles |
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BUPT_ART_Anbarasan_f.pdf | 935.75 kB | Adobe PDF | View/Open |
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