Abstract:
This paper presents a new procedural design
sequence for the design of a CMOS current conveyor. It
is based on the structured design approach and consists
in circuit partitioning, derivation of the specifications for
each basic analog structure, and step-by-step design.
BSIM2EKV converter is presented and EKV model is
used for hand calculations. PAD (Procedural Analog
Design) tool is used for validation. CCII step-by-step
design is presented. Simulations (for verification and
fine-tuning) using Mentor Graphics tools are presented.
