Procedural design of a CMOS current conveyor [articol]

dc.contributor.author	Drăgoi, Beniamin
dc.date.accessioned	2020-03-17T11:25:23Z
dc.date.accessioned	2021-03-01T08:39:00Z
dc.date.available	2020-03-17T11:25:23Z
dc.date.available	2021-03-01T08:39:00Z
dc.date.issued	2009
dc.identifier.citation	Drăgoi, Beniamin. Procedural design of a CMOS current conveyor. Timişoara: Editura Politehnica, 2009	en_US
dc.identifier.uri	http://primo.upt.ro:1701/primo-explore/search?query=any,contains,Procedural%20design%20of%20a%20CMOS%20current%20conveyor&tab=default_tab&search_scope=40TUT&vid=40TUT_V1&lang=ro_RO&offset=0 Link Primo
dc.description.abstract	This paper presents a new procedural design sequence for the design of a CMOS current conveyor. It is based on the structured design approach and consists in circuit partitioning, derivation of the specifications for each basic analog structure, and step-by-step design. BSIM2EKV converter is presented and EKV model is used for hand calculations. PAD (Procedural Analog Design) tool is used for validation. CCII step-by-step design is presented. Simulations (for verification and fine-tuning) using Mentor Graphics tools are presented.	en_US
dc.language.iso	en	en_US
dc.publisher	Timişoara: Editura Politehnica	en_US
dc.relation.ispartofseries	Seria electronică şi telecomunicaţii, Tom 54(68), fasc. 1 (2009);
dc.subject	Current conveyor	en_US
dc.subject	EKV model	en_US
dc.subject	PAD tool	en_US
dc.title	Procedural design of a CMOS current conveyor [articol]	en_US
dc.type	Article	en_US