Abstract:
In this paper, a hybrid Transmission Gate -
CMOS logic (TG-CMOS) single bit full adder is
proposed. This proposed full adder replaces the six
transistor XNOR in the existing adder with two transistors
XNOR and also the carry generation path is modified for
better power with good voltage swing. The proposed logic
is designed as single bit full adder and implemented with
a 16 bit ripple carry adder. The design and simulation are
done through cadence virtuoso tool with 180nm, 90nm
and 45nm technologies. The performance parameters of
the proposed design is compared with the existing adder
designs. The Performance analysis of the proposed system
shows that it consumed less power and operates in high
speed. Also the extended version of proposed full adder
ie., 16 bit ripple carry adder works effectively.
