Abstract:
Proportional-Integral-Derivative (PID) control is widely used in industries such as chemical, petrochemical, robotics etc, since this control algorithm has been universally accepted in most of the industrial control. There are many factors that makes PID controller most popular, such as its low cost, easy maintenance and its robustness in a large range of operating condition. Razor flip-flops are incorporated to improvise the PID’s performance, by detecting and correcting the timing errors on critical path. A novelty has been introduced in the proposed methodology, which involves a Flip Flop called Razor Clock Gated Flip Flop (RCGFF) by using Pulse-Triggered Flip-Flop. This proposed outlook reduces the timing error and improves the integrated sequential circuits’ robustness. RCGFF has been used to achieve high-precision, high-speed, power reduction in static and average power consumption in PID controller. This procedure is appropriate for low power and data communication in PID controller. The proposed RCGFF is associated with preceding work such as Semi-Dynamic Flip-Flop (SDFF), Dynamic Data Flip-Flop (DDFF), Hybrid Latch Flip-Flop (HLFF) and Clocked CMOS Flip-Flop (CCMOS) in terms of attributes like power consumption, Power Delay Product (PDP), time delay and area. Results are authenticated by simulations, the proposed method achieves 74% of power reduction comparing to conventional existing design, by means of IBM 130 nm with 1.8 supply voltage.
