Abstract:
In this paper, a new representation for Fast Fourier Transform (FFT) algorithms based on feedforward FFT architecture is proposed. A 4096 point pipelined Feedforward FFT processor is designed to achieve high throughput for Very high-speed Digital Subscriber Line (VDSL) and IEEE 802.16e standard applications. The proposed hardware architecture has been designed based on reducing the number of rotators and their complexity by finding the efficient distribution of FFT rotations. The proposed 2 - parallel, 4 - parallel and 8 - parallel radix-2k Feedforward MDC architecture is compared with previous FFT architectures. From the analysis the proposed 4- parallel architecture savings the area of rotators increased from 17% to 23% and the proposed 8- parallel architecture save around 23% to 29% with respect to the existing architectures.
