Abstract:
In modern VLSI technology, we get useful information accompanied with slightly erroneous outputs. To reduce the error, a novel error-tolerant approximate computing (ETAC) is proposed. The objective of this research is to develop a new approximate multiplier and utilize modified 4:2 compressor and discussed its performance. The usage of compressor in the proposed model will improve the efficiency and minimizes the processing time, since the power consumption and performance is generally depends on the area required for doing the operation. Using OR gate in the accumulation of column wise generate elements in the altered partial product matrix provides exact result in most of the cases. The power consumption and its silicon area reduced dramatically by 9.24% and 4.88% in the proposed multiplier compared with conventional Wallace multipliers.
