A new linear systolic array for the VLSI implementation of 2-D IDST [articol]

Abstract

In this paper a new linear VLSI array architecture for the VLSI implementation of the 2-D IDST based on a new systolic array algorithm is proposed. This new design approach uses a new efficient VLSI algorithm. It employs a new formulation of the inverse DST that is mapped on a linear systolic array. Using the proposed systolic array high computing speed is obtained with a low I/O cost. The proposed architecture is characterized by a small number of I/O channels located at the two extreme ends of the array together with a low I/O bandwidth that is independent of the transform length N. The topology of the proposed VLSI architecture is highly modular and regular and uses only local connections. Thus, it is well suited for a VLSI implementation