Improved linearity active resistor with negative equivalent resistance [articol]

Abstract

An original improved linearization technique for a CMOS active resistor will be further presented. The main advantages of the original proposed implementation are the improved linearity, the small area consumption and the improved frequency response. The new method for linearizing the I(V ) characteristic of the active resistor will be based on a parallel connection of two quasi-ideal circuits opposite excited and different biased, having the result of improving the circuit linearity with about an order of magnitude. Because of this original design technique, the circuit linearity is not affected by the second-order effects that alter the MOS transistor operation. The reduced complexity obtained by using a FGMOS transistor will be made maintaining the compatibility with classical technologies (the classical FGMOS device could be replaced by an original equivalent circuit using exclusively classical MOS devices). The frequency response of the circuit is very good as a result of operating all MOS transistors in the saturation region. In order to design a circuit having a negative equivalent resistance, an original method specific to the proposed implementation of the active resistor circuit will be presented. The circuit is implemented in 0.35µm CMOS technology, the SPICE simulation confirming the theoretical estimated results and showing a linearity error under a percent for an extended input range (±500mV) and for a small value of the supply voltage (±3V) .