Compensated CMOS delay cells over process, voltage and temperature variations [articol]

Abstract

One of the challenges in digital systems is the distribution of the generated on-chip clock with a small uncertainty. In this paper a high performance compensated delay cell concept it is presented. It is based on a current reference, which is almost insensitive to PVT (process, voltage and temperature) variations. Using this current reference the delay value of the compensated delay cell it is nearly constant over temperature range (-55C to 125C) and voltage range (1.62V to 1.98V). Post layout simulation results shows a ratio for the value of the delay between best case corner and worst case corner smaller than 1.5.