Please use this identifier to cite or link to this item: https://dspace.upt.ro/xmlui/handle/123456789/7131
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dc.contributor.authorRamani, G.-
dc.contributor.authorGeetha, K.-
dc.date.accessioned2025-02-10T10:45:59Z-
dc.date.available2025-02-10T10:45:59Z-
dc.date.issued2019-
dc.identifier.citationRamani,G.; Geetha,K.: A novel code compression approach for embedded risc processor. Timişoara: Editura Politehnica, 2019.en_US
dc.identifier.issn1582-4594-
dc.identifier.urihttps://dspace.upt.ro/xmlui/handle/123456789/7131-
dc.description.abstractNow a days most of the processors are high performance RISC processors .This paper introduces a novel code compression approach for embedded RISC processor, which reduces the code size and improves the compression ratio. Code compression is the technique to reduce the program size using various code compression algorithms to original instruction sets. There are two methods of compression is used in this paper. One is Dictionary based and the other is statistical compression. Our implementation is assessed through various benchmarking performed on embedded programs. In this approach, an efficient code compression is achieved using lookup table and Canonical Huffman decoder.en_US
dc.language.isoenen_US
dc.publisherTimișoara : Editura Politehnicaen_US
dc.relation.ispartofseriesJournal of Electrical Engineering;Vol 19 No 1-
dc.subjectRISC processorsen_US
dc.subjectStatistical compressionen_US
dc.subjectDictionary based compressionen_US
dc.subjectCode compressionen_US
dc.titleA novel code compression approach for embedded risc processor [articol]en_US
dc.typeArticleen_US
Appears in Collections:Articole științifice/Scientific articles

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