Abstract:
Digital Filters are the significant component required in most DSP (digital signal processing) applications. This proposed work plays a significant role in low power consumption and reduction in area. Several researchers studied and investigated about reducing the switching activity of the adder blocks and their approaches do not provide better accuracy. To obtain high throughput, as well as low power and area consumption, an improved architecture for efficient Unified Adder/Subtractor (UAS) based Carry SeLect Adder(CSLA) Adder/Subtractor implementation of the digital signal processing parts are preferable. This method performs simultaneous calculation of sum and difference of two operands with less area and low power. This Unified Adder/Subtractor reduces the power consumption of the circuit with at least one order of magnitude compared to a flexible implementation using digital signal processors. The proposed technique helps in reducing the area and power consumption for different orders of filter by 58.5% and 64.9% respectively. The experimental results of Finite Impulse Response (FIR) in the range of 10 -100 taps and the coefficients of 8, 12 and 16 shows the improvement results when compared to the canonical signed digit based vertical and horizontal common sub-expression elimination (VHCSE) algorithm. The simulation results are obtained with the help of Cadence RC tool in TSMC 180 nm technology.
