Abstract:
Scan design provides controllability and observability of internal state variables for the circuit under test and also converts a sequential circuit problem into a combinational one by partitioning the circuit in testing process. Scan design with multiple latches and multiple clocks emerge as a solution for clock skew, jitter issues in contemporary design. Later single-clock, single-latch Level Sensitive Scan Design (LSSD) emerge as the scannable cell for latches, in low power and high performance designs. Recently Tri-state LSSD (TLSSD) emerges with less number of transistors and offers less power consumption than original LSSD. In this paper, an LSSD scan cell which consumes less power and area compared with original single latch LSSD and Tri-state LSSD (TLSSD) is proposed. The proposed LSSD extension of TLSSD has better trade-offs between number of transistors, area and power of less than 28 % compared to the existing TLSSD.
