CMOS multiplier circuit with improved linearity [articol]

Abstract

An original voltage multiplier circuit will be presented. The circuit is implemented in 0.35 µm CMOS technology and, in order to improve its frequency response, it is based exclusively on MOS transistors working in saturation region. The utilization of a FGMOST (Floating Gate MOS Transistor) for replacing the classical MOS devices allows obtaining an important reduction of the circuit complexity and, as a result, of the silicon occupied area. The SPICE simulation using the previous mentioned technological parameters confirms the theoretical estimated results, showing an excellent linearity of the new proposed CMOS voltage multiplier circuit.