Design and performance analysis of single bit full adder circuit using hybrid technique [articol]

Abstract

In this paper, an enhanced single bit full adder circuit is designed using hybrid technique. The hybrid technique is formed by replacing the n-MOS pull down network of constant delay logic with p-MOS pull up network. In the integrated design, the propagation delay of the signals which affect the performance of the circuit and the excessive power dissipation discourages their use in the systems. The glitches are a major component to increase the power consumption and delay in the complex circuit such as arithmetic operations. The proposed hybrid technique is used to remove the glitches in digital circuits which reduce delay, power and has high performance. Delay and Power–delay product is minimized than previous technologies. The 0.25um technology is used to design a circuit. The circuit simulated by using Tanner EDA Tool, 13v. The applied voltage is 1.0V. The simulation result illustrates that the hybrid design techniques have 27.8% of delay reduction compared to dynamic domino logic design and work at a speed of 0.499GHz.